Memory arbiter synthesis and verification for a radar memory interface card

Memory arbiter synthesis and verification for a radar memory interface card

Article

Ernits, Juhan

Published in: Nordic journal of computing 12 (2005) : 2, s. 68-88

Saved in:

Language

English

Classification

acmccs B.8.2
acmccs C.4
acmccs D.2.2

Subjects/keywords

formal analysis

bit-state hashing

hardware synthesis

guided model checking