Memory arbiter synthesis and verification for a radar memory interface card

Memory arbiter synthesis and verification for a radar memory interface card

Artikkeli

Ernits, Juhan

Julkaisussa: Nordic journal of computing 12 (2005) : 2, s. 68-88

Tallennettuna:

Kieli

englanti

Luokitus

acmccs B.8.2
acmccs C.4
acmccs D.2.2

Aiheet/asiasanat

formal analysis

bit-state hashing

hardware synthesis

guided model checking

Saatavuustiedot

Henkilökuntanäyttö